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C9950
3.3V, 180-MHz, Multi-Output Clock Driver
Product Features
* * * * * * * * * 180-MHz Clock Support Supports PowerPCTM, Intel(R), and RISC Processors 9 Clock Outputs: Frequency Configurable Oscillator or Crystal Reference Input Output Disable Control Spread Spectrum Compatible Pin Compatible with MPC950 Industrial Temp. Range: -40C to +85C 32-Pin TQFP Package Table 1. Frequency Table[1] FB_SEL = 1 SEL (A:D) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 QA 4x 4x 4x 4x 4x 4x 4x 4x 2x 2x 2x 2x 2x 2x 2x 2x QB 2x 2x 2x 2x x x x x 2x 2x 2x 2x x x x x QC (0,1) 2x 2x x x 2x 2x x x 2x 2x x x 2x 2x x x QD (0:4) 2x x 2x x 2x x 2x x 2x x 2x x 2x x 2x x FB_SEL = 1 QA QB 8x 8x 8x 8x 8x 8x 8x 8x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 4x 2x 2x 2x 2x 4x 4x 4x 4x 2x 2x 2x 2x QC (0,1) 4x 4x 2x 2x 4x 4x 2x 2x 4x 4x 2x 2x 4x 4x 2x 2x QD (0:4) 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x 4x 2x
Note: 1. x = is the reference input frequency
Block Diagram
SELA PLL_EN TCLK REF_SEL VCO 200480MHz
Pin Configuration
LPF 8/ 16 FB_SEL SELB SELC MR/OE#
4/ 8
QB
4/ 8
QC0 QC1
VDD FB_SEL SELA SELB SELC SELD VSS XIN
1 2 3 4 5 6 7 8
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
XIN XOUT
OSC
Phase Detector
2/ 4
QA
REF_SEL PLL_EN TCLK VSS QA VDDC QB VSS
C9950
9 10 11 12 13 14 15 16
QC0 VDDC QC1 VSS QD0 VDDC QD1 VSS
Power-On Reset 4/ 8 QD0 QD1
SELD
QD2 QD3 QD4
Cypress Semiconductor Corporation Document #: 38-07072 Rev. *C
*
3901 North First Street
*
San Jose
XOUT MR/OE# VDDC QD4 VSS QD3 VDDC QD2
*
CA 95134 * 408-943-2600 Revised December 21, 2002
C9950
Pin Description[2]
Pin 8 9 30 28 26 22, 24 12, 14, 16, 18, 20 2 Name XIN XOUT TCLK QA QB QC(1,0) QD(4:0) FB_SEL VDDC VDDC VDDC VDDC PWR I/O I 0 I O O O O I PD Type Description Oscillator Input. Connect to a crystal. Oscillator Output. Connect to a crystal. External Test Clock Input. Clock Output. See Frequency Table. Clock Output. See Frequency Table. Clock Outputs. See Frequency Table. Clock Outputs. See Frequency Table. Feedback Select Input. If FB_SEL = 1, then the (/8) counter is selected in the PLL feedback loop. If FB_SEL = 0, then the (/16) counter is selected in the PLL feedback loop. Master Reset/Output Enable Input. When asserted HIGH, resets all of the internal flip-flops and also disables all of the outputs. When pulled LOW, releases the internal flip-flops from reset and enables all of the outputs. PLL Enable Input. When asserted HIGH, PLL is enabled. And when set LOW, PLL is bypassed. Reference Select Input. When HIGH, TCLK is the reference clock and when LOW, the crystal oscillator is selected. Frequency Select Inputs. See Frequency Table. If SEL_ = 1, then QA divider = /4, QB:D divider = /8 If SEL_ = 0, then QA divider = /2, QB:D divider = /4 3.3V Power Supply for Output Clock Buffers. 3.3V Power Supply for PLL Common Ground
10
MR/OE#
I
31 32 3, 4, 5, 6
PLL_EN REF_SEL SEL(A:D)
I I I
11, 15, 19, 23, 27 1 7, 13, 17, 21, 25, 29
VDDC VDD VSS
Note: 2. PD = Internal Pull-Down, PU = Internal Pull-Up.
Document #: 38-07072 Rev. *C
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C9950
Description
The C9950 has an integrated PLL that provides low skew and low jitter clock outputs for high-performance microprocessors. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz and 480 MHz. This allows a wide range of output frequencies from 25 MHz to 180 MHz. The internal VCO frequency is divided by 8 or 16 and compared to the input reference clock. These selectable dividers allow for input reference clock flexibility. The internal VCO is running at 2x or 4x the high speed output (QA), and 4x or 8x the outputs Q(B:D) depending on the configuration (see Table 2). The use of even dividers ensures that the output duty cycle remains at 50%.
Output Frequency
The C9950 generates outputs with programmable frequency relationships. As a result, the input reference frequency is a function of the desired output frequency (Table 1). The following block diagram illustrates the corresponding parameters that are needed to calculate the output frequency.
Fref
Phase Detector LPF
VCO
/N
Qn
/m
Figure 1. Fref = FVCO/m, FVCO = FQn x N Fref = (FQn x N) / m Where m = 8 (FB_SEL = 1) or m = 16 (FB_SEL = 0), and N = 2, 4, or 8 depending on SEL_ as shown in Table 1. Table 2.
INPUTS SELA 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SELB 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SELC 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SELD 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 QA VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 VCO/4 QB
OUTPUTS QC VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 QD VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/8 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8
Document #: 38-07072 Rev. *C
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C9950
Table 3. Suggested Oscillator Crystal Parameters Parameter TC TS TA CL RESR Description Frequency Tolerance Note 1 Conditions Min. Typ. 20 40 Max. 100 100 5 80 Unit PPM PPM PPM/Yr pF Ohms
Frequency Temperature (TA -10 to +60C)[3] Stability Aging Load Capacitance Effective Series Resistance (ESR) (first 3 years @ 25C)[3] The crystal's rated load Note 4
[3]
Notes: 3. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meets or exceeds these specifications 4. Larger values may cause this device to exhibit oscillator startup problems
Document #: 38-07072 Rev. *C
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C9950
Maximum Ratings[5]
Maximum Input Voltage Relative to VSS: ............ VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................-65C to + 150C Operating Temperature: ................................ -40C to +85C Maximum ESD protection .............................................. 2 KV Maximum Power Supply: ................................................5.5V Maximum Input Current:..................................................20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
DC Parameters: VDD = VDDC = 3.3V 5%, TA = -40C to +85C
Parameter VIL VIH IIL IIH VOL VOH IDDC IDD Cin Description Input Low Voltage Input High Voltage Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Output Low Voltage Output High Voltage Quiescent Supply Current PLL Supply Current Input Capacitance Note 6 Note 6 IOL = 40 mA, Note 7 IOH = -40 mA, Note 7 All VDDC and VDD VDD only 2.4 15 15 20 20 4 2.0 -120 120 0.5 Conditions Min. Typ. Max. 0.8 Unit V V A A V V mA mA pF
AC Parameters[8]: VDD = VDDC = 3.3V 5%, TA = -40C to +85C
Parameter Tr/Tf Fref Fxtal FrefDC Fvco Tlock Tr/Tf Fout Description TCLK Input Rise/Fall Reference Input Frequency Crystal Oscillator Frequency Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time Output Clocks Rise/Fall Time Maximum Output Frequency
[10]
Conditions
Min. Note 9
Typ.
Max. 3.0 Note 2 25 75 480 10 1.0 180 120 60
Unit ns MHz MHz % MHz ms ns MHz
See Table 3 for details
10 25 200
0.8V to 2.0V QA = (/2) QA/QB = (/4) QB = (/8)
0.10
FoutDC tpZL, tpZH tpLZ, tpHZ TCCJ TSKEW0
Output Duty Cycle Output enable time (all outputs) Output disable time (all outputs) Cycle to Cycle Jitter (peak to peak)[10] Any Output to Any Output Skew
[10]
TCYCLE/2 - 1
TCYCLE/2 + 1 6 7 100 200 350
ns ns ns ps ps
Notes: 5. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 6. Inputs have internal pull-up/pull-down resistors that affect input current. 7. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission. Output buffers are dual staged to control drive strength in order to reduce over / under shoot. 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. 9. Maximum and minimum input reference is limited by the VCO lock range. 10. Outputs loaded with 30 pF each.
Document #: 38-07072 Rev. *C
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C9950
Package Drawing and Dimensions 32-Pin TQFP Outline Dimensions
Inches Symbol A A1 D
D
Millimeters Max. 1.200 1.050 9.050 7.050 0.45 0.75 Min. 0.039 0.037 0.352 0.274 0.012 0.018 Nom. 0.043 0.039 0.354 0.276 0.015 0.024 Max. 0.047 0.041 0.356 0.278 0.018 0.030
Min. 1.000 0.950 8.950 6.95 0.30 0.45
Nom. 1.100 1.000 9.000 7.000 0.37 0.80 BSC 0.600
D1 b e L
0.031 BSC
D1 12 A1
L
e
b
Ordering Information
Part Number[11] C9950AA Package Type 32-Pin TQFP Production Flow Industrial, -40C to +85C
Note: 11. The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below.
Marking: Example:
Cypress C9950AA Date Code, Lot #
C9950AA
Package A = TQFP Revision Device Number
Document #: 38-07072 Rev. *C
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
C9950
Document Title: C9950 3.3V, 180-MHz, Multi-Output Clock Driver Document Number: 38-07072 REV. ** *A *B *C ECN NO. 107108 108125 109802 122757 Issue Date 06/11/01 07/03/01 02/08/02 12/22/02 Orig. of Change IKA NDP DSG RBI Description of Change Convert from IMI to Cypress Delete Pull Down in Pin 10, 30, & 32 and Pull Up in Pin 3, 4, 4, 5, 6, & 31(See page 2) Convert from Word to Frame Add power up requirements to maximum ratings information
Document #: 38-07072 Rev. *C
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